1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a transistor of a semiconductor device.
2. Background of the Related Art
Most semiconductor devices comprise transistors. FIGS. 1a through 1e illustrate, in cross-sectional views, the process steps for forming a transistor in a semiconductor device according to a conventional art. Referring to FIG. 1a, a substrate 10 with device isolation layers 12 is provided and an ion implantation is performed on the substrate 10 in order to adjust a threshold voltage. Referring to FIG. 1b, a gate electrode 16 is formed on the substrate 10. Then, a first source/drain region 18 with shallow junction is formed in the substrate 10 by performing an ion implantation using the gate electrode 16 as a mask. Referring to FIGS. 1c and 1d, an insulating layer 20 is deposited over the substrate 10 with the gate electrode 16. Then, an etching process is performed on the insulating layer 20 to form spacers 22 on sidewalls of the gate 16. Referring to FIG. 1e, an ion implantation is performed using the spacers as a mask to form a second source/drain region 30 with deep junction in the substrate 10. Thus, the transistor formed according to the above-mentioned processes comprises the gate electrode 16 and source/drain regions consisting of the first source/drain region 18 and the second source/drain region 30.
As a prior art, U.S. Pat. No. 6,238,988, Hsiao and Tseng, discloses a method of forming a MOS (metal oxide semiconductor) transistor. In the method according to the above-mentioned U.S. patent, a gate is first formed on the silicon substrate of the semiconductor wafer and, then, a first spacer made of silicon nitride and the LDD are formed adjacent to the gate. A conductive layer is formed on the semiconductor wafer that forms a corner on the conjoining section of the spacer and the silicon substrate. A spacer made of silicon oxide is formed on the corner of the conductive layer and, then, an etching process is performed to remove the conductive layer above the gate and the silicon substrate. The conductive layer on the corner adjacent to the first spacer remains. Finally, the spacer made of silicon oxide is completely removed, and an ion implantation process is performed to form a source/drain region on the silicon substrate adjacent to the conductive layer.
As another prior art, U.S. Pat. No. 5,864,163, Chou and Sun, discloses a method of fabricating a MOS device. The method of fabricating a MOS device comprises the steps of forming a gate oxide over a substrate; depositing a first polysilicon layer over the gate oxide; implanting a threshold adjust dopant of a first conductivity type through the polysilicon layer, through the gate oxide and into the substrate; depositing a second layer of gate material over the first polysilicon layer; and forming a gate electrode mask and etching the second layer of gate material to form a gate electrode. In addition, this method also includes the following steps performed before the formation of the gate oxide: forming a sacrificial oxide layer on a surface of the substrate; implanting into the substrate a dopant of a second conductivity type; and etching the sacrificial oxide to expose the surface of the substrate.
However, the above-mentioned conventional methods of fabricating a transistor can cause the following problems. First, ions in the first source/drain region can be diffused because of a thermal process performed during a process of forming spacers after forming the first source/drain region. Therefore, effective channel length becomes shorter than the channel length determined based on formation of a gate, that is, a short channel effect occurs. Second, when an ion implantation is performed to form the source/drain region, out-diffusion of ions, which are implanted into the substrate to adjust a threshold voltage, occurs because the ions implanted to adjust the threshold voltage are generally light and the ions implanted to form the source/drain region are heavy. In other words, when heavy ions are implanted, they collide with light ions and the light ions are scattered. Therefore, concentration of the ions to adjust the threshold voltage is lowered due to the out-diffusion and thereby a reverse short channel effect is caused.